A-DATA Memory 256MB PC4200 DDR2 SDRAM DIMM 240-pin 533MHz

A-DATA Memory 256MB PC4200 DDR2 SDRAM DIMM 240-pin 533MHz

A-DATA offers 533- MHz DDRII Registered DIMMs in capacities up to 512MB. DDRII modules features faster speeds of up to 667 MHz, higher data bandwidths, lower power consumption by about 50 percent, and enhanced thermal performance versus DDRI ones. DDRII memory chips will be in FBGA (Fine-pitch BGA) chip packages, and will incorporate On-Die Termination (ODT) to minimize memory signal reflections at high speeds, thereby improving timing margins. In addition, DDR2 memory chips will DDR2 memory chips will come in capacities up to 4 Gigabits, allowing for higher-capacity modules. To prevent accidental insertion into an incompatible motherboard, DDR2 modules have a unique key or notch in their connector that must match the memory socket.Vitesta DDRII modules can be used on desktops to improve overall performance.

Status: Active

MPN: ADT-256-D2-533

Vendor: A-DATA

Key Features

Storage Capacity 256 MB

Manufacturer Warranty 1 year warranty

Bus Clock Rate 533MHz

Technology DDR2

Form Factor 240-pin DIMM

Detail Specifications

DDR2 archieves the high-speed by four times the transmission amount of data . It also doubles the data rate of DDR. In the 4-bit prefetch architecture, READ or WRITE can achieve the four times the amount of data in a really internal bus clock. This is why the DDR2 can operate in four times faster than the internal operation frequency.

In DDR2, it is composed the termination resistor inside which is applied to match the transmission impedance on the mainboard. It will greatly attenuate the reflected noise resulted from last signals which improves a clear logic-level to avoid the reception of error data.

OCD is the Input/Output driver resistance which applied to adjust the cross-voltage to equalize the pull-up and pull-down signal. It will greatly help to the noise-rejected quality from DDR2 module to chipset in mainboard.

In a posted CAS (Column Address Strobe) operation, a CAS signal (READ/WRITE command) can be input to the next clock after RAS (Row Address Strobe) signal (active command) input. The CAS command is held by the module side and executed after the additive latency (0, 1, 2, 3 and 4). It is easier controller design by avoiding collision on the command bus, and improves the command and data bus efficiency due to simple command order. It also improves the practical memory bandwidth by removing the bubble.